Conventional cesium atomic oscillators and rubidium atomic oscillators have been developed. These oscillators are used to generate a highest-level reference clock, which is a reference clock at a highest level, and are also used in GPS (Global Positioning System) to generate and transmit a 1PPS (1 pulse per second) signal, which is a reference clock generated based on the highest-level reference clock. Furthermore, there has been provided a clock generating apparatus (e.g., a PLL (Phase Locked Loop) circuit) for generating an output clock used by a device in a digital synchronous network by synchronizing a 1PPS signal transmitted from a GPS and an operation clock generated by an internal high-precision oscillator (see Japanese Laid-open Patent Publication No. 2005-244648, Japanese Laid-open Patent Publication No. 2006-217203 and Japanese Laid-open Patent Publication No. 2007-27809).
An overview of a conventional clock generating apparatus is explained here with reference to FIG. 8. FIG. 8 is a diagram for explaining the overview of a conventional clock generating apparatus. Incidentally, it will be assumed that an output clock synchronized with a 1PPS signal is generated by the conventional clock generating apparatus composed of a phase comparator (e.g., a DPD: digital phase detector), a loop filter (e.g., a DLF: digital loop filter), an oscillator (e.g., a DDS: direct digital synthesizer), a multiplier (e.g., an analog PLL circuit), a divider, and an internal high-precision oscillator.
When receiving a 1PPS signal (see (1) in FIG. 8), the phase comparator of the conventional clock generating apparatus measures the difference in phase between both the 1PPS signal and a feedback clock with a high-speed clock (see (2) in FIG. 8). The high-speed clock here means a clock obtained from an output clock previously generated by the clock generating apparatus by being multiplied by the multiplier (see (3) in FIG. 8). The feedback clock here means a clock obtained from an output clock previously generated by the clock generating apparatus by being divided by the divider (see (4) in FIG. 8).
Next, the loop filter of the conventional clock generating apparatus averages the phase difference measured by the phase comparator (see (5) in FIG. 8).
Then, the oscillators of the conventional clock generating apparatus generate an output clock of a new frequency synchronized with the 1PPS signal (see (7) in FIG. 8) by using an operation clock generated by the internal high-precision oscillator (see (6) in FIG. 8) and the averaged phase difference averaged by the loop filter. The output clock of the new frequency is then returned to the multiplier and the divider (see (8) in FIG. 8).
In this manner, the conventional clock generating apparatus feeds back an output clock thereby generating an output clock synchronized with a 1PPS signal.
However, the conventional technology described above has a problem in that the operation of other devices in a digital synchronous network may be adversely affected.
Namely, in a process of generating a new output clock with a difference in phase between a reference clock and an output clock, for example, if the reference clock is a 1PPS signal, the conventional oscillator generates an output clock of a new frequency every 1 second (see (A) in FIG. 8). At this time, in the conventional technologies, an output clock with a frequency that greatly fluctuates is generated; thus, the operation of other devices in the digital synchronous network that uses this output clock are adversely affected.